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| SPANSION Flash Memory Data Sheet TM September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-20901-1E PAGE MODE FLASH MEMORY CMOS 128M (8M x 16/4M x 32) BIT MBM29XL12DF-70/80 s DESCRIPTION The MBM29XL12DF is 128M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M words by 16 bits or 4M words by 32 bits. The device is offered in 90-pin SSOP and 96-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V Vcc supply. 12.0 V Vpp and 5.0 V Vcc are not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINEUP Part No. Ordering Part Number Suffix VCC (V) Max Random Address Access Time (ns) Max Page Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) 70 3.0 to 3.6 70 25 70 25 MBM29XL12DF 80 2.7 to 3.1 80 30 80 30 s PACKAGES 90-pin plastic SSOP 96-ball plastic FBGA (FPT-90P-M01) (BGA-96P-M02) MBM29XL12DF-70/80 (Continued) The device provides truly high performance non-volatile Flash memory solution. The device offers fast page access times of 25 ns and 30 ns with random access times of 70 ns and 80 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The page size is 8 words or 4 double words. The dual operation function provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the program and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded ProgramTM Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 0.5 seconds. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits program and erase operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29XL12DF-70/80 s FEATURES * 0.17 m Process Technology * Single 3.0 V Read, Program and Erase Minimized system level power requirements * Simultaneous Read/Write (Program and Erase) Operations (Dual Bank) * FlexBankTM *1 Bank A: 16 Mbit (4K words x8 and 32K words x31) Bank B: 48 Mbit (32K words x96) Bank C: 48 Mbit (32K words x96) Bank D: 16 Mbit (4K words x8 and 32K words x31) * High Performance Page Mode 25 ns maximum page access time at VCC = 3.0 V to 3.6 V(70 ns random access time) 30 ns maximum page access time at VCC = 2.7 V to 3.1 V(80 ns random access time) * 8 Words Page (x16) / 4 Double Words Page (x32) Size x x * Compatible with JEDEC-Standard Commands Uses same software commands as E2PROMs * Compatible with JEDEC-standard World-wide Pinouts 90-pin SSOP (Package Suffix : PFV) 96-ball FBGA (Package Suffix : PBT) * Minimum 100,000 Program/Erase Cycles * Sector Erase Architecture Eight 4K words, two hundred fifty -four 32K words, and eight 4K words sectors Any combination of sectors can be concurrently erased. Also supports full chip erase * Dual Boot Block 16 by 4K words bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range * HiddenROM Region 128 words of HiddenROM region by using device address of word mode 000000h to 00007Fh (double word mode: 000000h to 00003Fh) accessible through a "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * Write Protect Pin (WP) Write Protect (WP) function allows protection of "outermost" 2x 4K words on both ends of boot sectors, x regardless of sector protection/unprotection status * Accelerate Pin (ACC) At VACC, increases program performance * Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector * Embedded ProgramTM *2 Algorithms Automatically programs and verifies data at specified address * Data Polling and Toggle Bit Feature for detection of program or erase cycle completion * Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode. * Low VCC Write Inhibit VLKO (Continued) 3 MBM29XL12DF-70/80 (Continued) * Program Suspend/Resume Suspends the program operation to allow a read in another word * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * In accordance with CFI (Common Flash Memory Interface) * Hardware Reset Pin (RESET) Hardware method to reset the device for reading array data * New Sector Protection Persistent Sector Protection Password Sector Protection * Hardware Sector Group Protection Hardware method disables any combination of sectors from program or erase operation *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 4 MBM29XL12DF-70/80 s PIN ASSIGNMENTS SSOP (TOP VIEW) N.C. N.C. N.C. RESET RY/BY A0 A1 A2 A3 A4 A5 VCC DQ0 DQ16 DQ1 DQ17 Vss VCC DQ2 DQ18 DQ3 DQ19 DQ4 DQ20 DQ5 DQ21 Vss VCC DQ6 DQ22 DQ7 DQ23 Vss A6 A7 A8 A9 A10 A11 A12 N.C. N.C. N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 N.C. N.C. ACC WP WE N.C. A21 A20 DW/W OE CE Vss DQ31/A-1 DQ15 DQ30 DQ14 Vss VCC DQ29 DQ13 DQ28 DQ12 DQ27 DQ11 DQ26 DQ10 Vss VCC DQ25 DQ9 DQ24 DQ8 VCC A19 A18 A17 A16 A15 A14 A13 N.C. N.C. N.C. N.C. N.C. (FPT-90P-M01) (Continued) 5 MBM29XL12DF-70/80 (Continued) FBGA (TOP VIEW) Marking Side A11 N.C. B11 N.C. C11 N.C. E10 DQ30 D9 CE D8 A20 D7 WE D6 E9 VSS E8 DW/W E7 N.C. E6 F10 VCC F9 DQ15 F8 OE F7 G10 DQ13 G9 DQ29 G8 DQ14 G7 H10 DQ12 H9 DQ28 H8 VSS H7 J10 DQ27 J9 DQ11 J8 DQ10 J7 N.C. J6 N.C. J5 N.C. J4 DQ5 J3 DQ4 J2 DQ20 K10 DQ26 K9 VSS K8 DQ25 K7 DQ8 K6 N.C. K5 A12 K4 DQ21 K3 DQ6 K2 VSS L10 VCC L9 DQ24 L8 A18 L7 A15 L6 N.C. L5 A11 L4 A8 L3 DQ7 L2 VCC M10 DQ9 M9 VCC M8 A17 M7 A14 M6 N.C. M5 A9 M4 A6 M3 DQ23 M2 DQ22 N9 A19 N8 A16 N7 A13 N6 N.C. N5 A10 N4 A7 N3 VSS P11 N.C. Q11 N.C. R11 N.C. A21 DQ31/A-1 N.C. F6 WP F5 A3 F4 DQ0 F3 DQ1 F2 DQ17 G6 RY/BY G5 A0 G4 DQ16 G3 VSS G2 VCC H6 N.C. H5 DQ2 H4 DQ18 H3 DQ19 H2 DQ3 RESET ACC D5 A1 D4 A4 E5 A2 E4 A5 E3 VCC A1 N.C. B1 N.C. C1 N.C. P1 N.C. Q1 N.C. R1 N.C. (BGA-96P-M02) 6 MBM29XL12DF-70/80 s PIN DESCRIPTIONS MBM29XL12DF Pin Configuration Pin A21 to A0, A-1 DQ31 to DQ0 CE OE WE RESET RY/BY DW / W WP ACC N.C. VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Reset / Temporary Sector Group Unprotection Ready/Busy Output Selects 32-bit or 16-bit mode Hardware Write Protection Program Acceleration Pin Not Connected Internally Device Ground Device Power Supply Function 7 MBM29XL12DF-70/80 s BLOCK DIAGRAM VCC VSS Bank A address A21 to A0, A-1 Y-Gating Cell Matrix 16 Mbit (Bank A) X-Decoder Cell Matrix 48 Mbit (Bank B) X-Decoder Bank B Address RESET WE CE OE DW/W WP ACC DQ15 to DQ0 State Control & Command Register RY/BY Status Control Bank C Address DQ31 to DQ0 X-Decoder Y-Gating Cell Matrix 16 Mbit (Bank D) X-Decoder Cell Matrix 48 Mbit (Bank C) Y-Gating Bank D address s LOGIC SYMBOL A-1 22 A21 to A0 DQ31 to DQ0 RESET CE OE WE DW/W WP ACC RY/BY 32 or 16 8 Y-Gating MBM29XL12DF-70/80 s DEVICE BUS OPERATION MBM29XL12DF User Bus Operations Table (DW/W = VIL) Operation Autoselect Manufacturer Code *1 Autoselect Device Code *1 Extended Autoselect Device Code *1 Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection *2,*4 Verify Sector Group Protection *2, *4 Boot Block Sector Write Protection *5 Temporary Sector Group Unprotection *6 Reset CE OE WE WP L L L L L H L L L L X X X L L L L L X H H VID L X X X H X X X H H H H H X H L X X X X X X X X X H L H X DQ31 A0 /A-1 L L L L A-1 X X A-1 L L X X X L H L H A0 X X A0 L L X X X A1 L L H H A1 X X A1 H H X X X A2 L L H H A2 X X A2 L L X X X A3 L L H H A3 X X A3 H H X X X A4 X X X X A4 X X A4 H H X X X A5 X X X X A5 X X A5 H H X X X A6 L L L L A6 X X A6 L L X X X A9 VID VID VID VID A9 X X A9 VID VID X X X DQ15 to RESET DQ0*7 Code Code Code Code DOUT High-Z High-Z DIN X Code X X High-Z H H H H H H H H H H H VID L Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See "sDC CHARACTERISTICS" for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29XL12DF Command Definitions Table". *2 : Refer to section on "Sector Group Protection". *3 : WE can be VIL if OE is VIL, OE at VIH initiates the program and erase operations. *4 : VCC = 3.0 V to 3.6 V for 70 ns random access time VCC = 2.7 V to 3.1 V for 80 ns random access time *5 : Protects "outermost" 2 x 4K words on both end of the boot block sectors. (SA0, SA1, SA268, and SA269) *6 : Also used for "Extended Sector Group Protection". *7 : DQ30 to DQ16 = X (VIL or VIH) 9 MBM29XL12DF-70/80 MBM29XL12DF User Bus Operations Table (DW/W = VIH) Operation Autoselect Manufacturer Code *1 Autoselect Device Code *1 Extended Autoselect Device Code *1 Read * 3 CE OE WE L L L L L H L L L L X X X L L L L L X H H VID L X X X H X X X H H H H H X H L WP X X X X X X X X X H L H X A0 L H L H A0 X X A0 L L X X X A1 L L H H A1 X X A1 H H X X X A2 L L H H A2 X X A2 L L X X X A3 L L H H A3 X X A3 H H X X X A4 X X X X A4 X X A4 H H X X X A5 X X X X A5 X X A5 H H X X X A6 L L L L A6 X X A6 L L X X X A9 VID VID VID VID A9 X X A9 VID VID X X X DQ31 to RESET DQ0 Code Code Code Code DOUT High-Z High-Z DIN X Code X X High-Z H H H H H H H H H H H VID L Standby Output Disable Write (Program/Erase) Enable Sector Group Protection *2,*4 Verify Sector Group Protection *2, *4 Boot Block Sector Write Protection *5 Temporary Sector Group Unprotection *6 Reset Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See "sDC CHARACTERISTICS" for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29XL12DF Command Definitions Table". *2 : Refer to section on "Sector Group Protection". *3 : WE can be VIL if OE is VIL, OE at VIH initiates the program and erase operations. *4 : VCC = 3.0 V to 3.6 V for 70 ns random access time VCC = 2.7 V to 3.1 V for 80 ns random access time *5 : Protects "outermost" 2 x 4K words on both end of the boot block sectors. (SA0, SA1, SA268, and SA269) *6 : Also used for "Extended Sector Group Protection". 10 MBM29XL12DF-70/80 MBM29XL12DF Command Definitions Table Command Sequence Read/Reset *1 Read/Reset *1 Autoselect DW W DW W Bus Second Seventh First Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Write Cycle Bus Bus Write Cycle Read/Write Write Cycle Write Cycle Write Cycle CyWrite Cycle Cycle cles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 2 4 XXXh F0h RA 2AAh RD 55h -- 555h AAAh -- F0h -- RA -- RD -- -- -- -- -- -- -- -- -- -- -- -- 555h AAAh AAh 555h 2AAh 3 555h AAAh AAh (BA) 555h 90h 55h AAAh -- -- -- -- -- -- -- -- 555h AAh AAh AAh B0h 30h AAh A0h 90h 2AAh Program Chip Erase Sector Erase DW W DW W DW W 4 6 6 1 1 3 2 2 555h AAAh 555h 2AAh 55h 55h 55h -- -- 55h PD 555h AAAh A0h 80h 80h -- -- 20h -- -- PA 555h AAAh PD AAh AAh -- -- -- -- -- -- 2AAh -- 55h 55h -- -- -- -- -- -- 555h AAAh -- 10h 30h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 555h AAAh 555h AAAh 555h 2AAh 555h 2AAh 555h AAAh 555h AAAh 555h AAAh 555h -- -- 2AAh 555h -- -- -- -- -- SA -- -- -- -- -- Program/Erase Suspend Program/Erase Resume Set to Fast Mode Fast Program *2 DW W DW W BA BA 555h AAAh XXXh XXXh -- -- 555h AAAh -- -- -- -- -- 555h PA -- -- DW Reset from 2 Fast Mode * W BA BA XXXh F0h XXXh *6 Extended Sector Group Protection*3 DW 4 W DW XXXh 60h SGA 60h SGA 40h SGA SD -- -- -- -- -- -- Query *4 W 1 (BA) 55h (BA) 55h 555h AAAh 98h -- -- -- -- -- -- -- -- -- -- -- -- HiddenROM DW Entry W HiddenROM DW Program *5 W HiddenROM DW Exit *5 W 3 4 4 AAh AAh AAh 2AAh 555h 2AAh 55h 55h 55h 555h AAAh 88h A0h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 555h AAAh 555h AAAh 555h 2AAh (HRA) PD PA 555h AAAh 555h AAAh 555h 90h XXXh 00h (Continued) 11 MBM29XL12DF-70/80 (Continued) Command Sequence HiddenROM DW Protect *5 W DW Bus Second Seventh First Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Write Cycle Bus Bus Write Cycle Read/Write Write Cycle Write Cycle Write Cycle CyWrite Cycle Cycle cles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 6 555h AAAh AAh 2AAh 555h 2AAh 55h 555h AAAh 60h OPBP 68h OPBP 48h XXXh XX0h PD0 XX1h PD1 38h XX0h PD0 XX1h PD1 XX2h PD2 XX3h PD3 -- -- -- -- RD (0) -- -- 555h 4 AAh AAAh 555h 55h Password Program *7 W -- -- -- 555h AAAh Password Unlock Password Verify DW W DW W 5 7 3 555h AAAh AAh AAh 2AAh 555h 2AAh 55h 55h 555h AAAh 28h XX0h PD0 XX1h PD1 C8h PWA PWD -- -- -- -- -- XX2h PD2 XX3h PD3 555h AAAh 555h AAAh 555h 2AAh -- -- RD (0) -- -- Password DW Mode Locking W Bit Program Persistent DW Sector Protection Mode Locking W Bit Program 555h 6 AAAh 555h 55h AAAh AAh 555h 2AAh 60h PL 68h PL 48h XXh -- -- 555h 6 AAAh 555h 55h AAAh AAh 555h 2AAh 60h SPML 68h SPML 48h XXh RD (0) -- -- PPB Program PPB Verify All PPB Erase *8 PPB Lock Bit Set PPB Lock Bit Verify DPB Write DPB Erase DPB/PPB Verify DW W DW W DW W DW W DW W DW W DW W DW W 6 4 6 3 555h AAAh AAh AAh AAh AAh 555h 2AAh 55h 55h 55h 55h 555h AAAh 60h 58h 60h 78h (SGA) WP SA EP -- 68h RD (0) 60h -- RD (1) X1h X0h RD (0) (SGA) WP -- EP -- 48h -- 40h -- XX -- XX -- RD (0) -- RD (0) -- -- -- -- -- -- -- -- -- 555h AAAh 555h AAAh 555h 2AAh 555h AAAh 555h AAAh 555h 2AAh 555h AAAh 555h AAAh 555h 2AAh 4 (BA) 555h 58h AAh 55h AAAh AAAh 555h 555h SA -- -- -- -- -- -- 4 4 555h AAAh AAh AAh 2AAh 555h 2AAh 55h 55h 555h AAAh 48h 48h SA SA -- -- -- -- -- -- -- -- -- -- -- -- 555h AAAh 555h AAAh 555h 2AAh 4 (BA) 555h 58h AAh 55h AAAh AAAh 555h 555h SA -- -- -- -- -- -- 12 MBM29XL12DF-70/80 Legend : RA PA = Address of the memory location to be read = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector BA = Bank Address RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SGA = Sector group address to be protected. Set sector group address and (A6, A5, A4, A3, A2, A1, A0) = (0, 1, 1, 1, 0, 1, 0) SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the HiddenROM area(Double Word Mode: 000000h to 00003Fh) (Word Mode : 000000h to 00007Fh) RD(0) = DQ0 data, RD(1) = DQ1 data. PPB Lock bit is read on DQ1 and PPB or DPB are read on DQ0. If set, DQ0/DQ1=1. If cleared, DQ0/DQ1=0. OPBP = (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 1, 0, 1, 0) 64 bit Password Data PD0 to PD1 : Double Word Mode PD0 to PD3 : Word Mode PWA/PWD = Password Address/Password Data PL = Password Locking Address (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 0, 1, 0, 1, 0) SPML = Persistent Protection Mode Locking (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 0, 0, 1, 0) WP = PPB Program (A6, A5, A4, A3, A2, A1, A0) is (0, 1, 1, 1, 0, 1, 0) EP = PPB Erase (A6, A5, A4, A3, A2, A1, A0) is (1, 1, 1, 1, 0, 1, 0) *1 : Both of these reset commands are equivalent. *2 : This command is valid during Fast Mode. *3 : This command is valid while RESET = VID. *4 : The valid addresses are A6 to A0. *5 : This command is valid during HiddenROM mode. *6 : The data "00h" is also acceptable. *7 : Data before fourth cycle also need to be programmed repearting from first cycle to third cycle. *8 : RD(0) of the sixth cycle shows PPB erase status. When RD(0) is "1", programming must be repeated from the beginning of first cycle to the fourth cycle; both fifth and the sixth validate full completion of erase. Notes : * Address bits A21 to A11 = X = "H" or "L" for all address commands except for PA, SA, BA, SGA, OPBP , PWA, PL, SPML, WP . * Bus operations are defined in "MBM29XL12DF User Bus Operations Table (DW/W = VIL)" and "MBM29XL12DF User Bus Operations Table (DW/W = VIH)". * The system should generate the following address patterns: DW (Double Word) Mode : 555h or 2AAh to addresses A10 to A0 W (Word) Mode : AAAh or 555h to addresses A10 to A0, A-1 * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. * Command combinations not described in "Command Definitions Table" are illegal. 13 MBM29XL12DF-70/80 MBM29XL12DF Autoselect Codes Table Type Manufacture's Code Device Code Extended Device Code*4 Double Word Word Double Word Word Double Word Word PPB Protection *1 : A-1 is for word mode. *2 : Sector Group can be protected by "Sector Group Protection", "Extended Sector Group Protection" and "New Sector Protection(PPB Protection)". Outputs 01h at protected PPB addresses and outputs 00h at unprotected PPB addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simutaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. *4 : At double word mode, a read cycle at address (BA) 01h (at word mode,02h) outputs device code. When 222227Eh (at word mode,227Eh) is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh (at word mode,1Ch), as well as at (BA) 0Fh (at word mode, 1Eh). A21 to A11 BA*3 BA*3 BA*3 BA*3 Sector Group Addresses A6 VIL VIL VIL VIL A5 x x x x A4 x x x x A3 VIL VIL VIH VIH A2 VIL VIL VIH VIH A1 VIL VIL VIH VIH A0 VIL VIH VIL VIH A-1*1 VIL x VIL x VIL x VIL VIL Code (HEX) 04h 2222227Eh 227Eh 2222220Dh 220Dh 22222200h 2200h 01h*2 VIL VIH VIH VIH VIL VIH VIL 14 MBM29XL12DF-70/80 Exteneded Auteselect Code Table Type Manufacturer's Code Device Code (DW) Code DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 04h 2222 227Eh A-1/0 0 A-1 0 0 0 HZ 0 HZ 0 HZ 0 0 0 1 HZ 1 HZ 1 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 1 HZ 1 HZ 1 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 1 HZ 1 HZ 1 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 0 1 HZ 1 HZ 1 HZ 0 0 0 0 HZ 0 HZ 0 HZ 0 0 (W) 227Eh (DW) 2222 220Dh Extended Device Code (W) 220Dh A-1 (DW) 2222 2200h 0 A-1 A-1/0 A-1/0 (W) 2200h PPB Protection PPB Unprotection Type Manufacturer's Code Device Code (DW) (W) (DW) 01h 00h Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h 2222 227Eh 227Eh 2222 220Dh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 (W) 220Dh Extended Device Code 2222 (DW) (W) 2200h 2200h 01h 00h PPB Protection * PPB Unprotection * HZ : High-Z (DW) : Double Word mode (W) : Word mode * : In word mode, DQ30 to DQ16 become "High-Z" and DQ31 becomes Lowest address "A-1". 15 MBM29XL12DF-70/80 Sector Address Tables (Bank A) Sector Size Bank Sector (KW / A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) Bank Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank A SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Sector Address (x 16) Address Range 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (x 32) Address Range 000000h to 0007FFh 000800h to 000FFFh 001000h to 0017FFh 001800h to 001FFFh 002000h to 0027FFh 002800h to 002FFFh 003000h to 0037FFh 003800h to 003FFFh 004000h to 007FFFh 008000h to 00BFFFh 00C000h to 00FFFFh 010000h to 013FFFh 014000h to 017FFFh 018000h to 01BFFFh 01C000h to 01FFFFh 020000h to 023FFFh 024000h to 027FFFh 028000h to 02BFFFh 02C000h to 02FFFFh 030000h to 033FFFh 034000h to 037FFFh 038000h to 03BFFFh 03C000h to 03FFFFh 040000h to 043FFFh 044000h to 047FFFh 048000h to 04BFFFh 04C000h to 04FFFFh 050000h to 053FFFh 054000h to 057FFFh 058000h to 05BFFFh 05C000h to 05FFFFh 060000h to 063FFFh 064000h to 067FFFh 068000h to 06BFFFh 06C000h to 06FFFFh 070000h to 073FFFh 074000h to 077FFFh 078000h to 07BFFFh 07C000h to 07FFFFh 16 MBM29XL12DF-70/80 Sector Address Tables (Bank B) Sector Address Sector Size (x 16) Bank Bank Sector Address (KW / Address Range A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank B SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh (x 32) Address Range 080000h to 083FFFh 084000h to 087FFFh 088000h to 08BFFFh 08C000h to 08FFFFh 090000h to 093FFFh 094000h to 097FFFh 098000h to 09BFFFh 09C000h to 09FFFFh 0A0000h to 0A3FFFh 0A4000h to 0A7FFFh 0A8000h to 0ABFFFh 0AC000h to 0AFFFFh 0B0000h to 0B3FFFh 0B4000h to 0B7FFFh 0B8000h to 0BBFFFh 0BC000h to 0BFFFFh 0C0000h to 0C3FFFh 0C4000h to 0C7FFFh 0C8000h to 0CBFFFh 0CC000h to 0CFFFFh 0D0000h to 0D3FFFh 0D4000h to 0D7FFFh 0D8000h to 0DBFFFh 0DC000h to 0DFFFFh 0E0000h to 0E3FFFh 0E4000h to 0E7FFFh 0E8000h to 0EBFFFh 0EC000h to 0EFFFFh 0F0000h to 0F3FFFh 0F4000h to 0F7FFFh 0F8000h to 0FBFFFh 0FC000h to 0FFFFFh 100000h to 103FFFh 104000h to 107FFFh 108000h to 10BFFFh 10C000h to 10FFFFh 110000h to 113FFFh 114000h to 117FFFh 118000h to 11BFFFh (Continued) 17 MBM29XL12DF-70/80 Sector Size Bank Sector (KW / A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) Bank Address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 Bank B SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Sector Address (x 16) Address Range 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh (x 32) Address Range 11C000h to 11FFFFh 120000h to 123FFFh 124000h to 127FFFh 128000h to 12BFFFh 12C000h to 12FFFFh 130000h to 133FFFh 134000h to 137FFFh 138000h to 13BFFFh 13C000h to 13FFFFh 140000h to 143FFFh 144000h to 147FFFh 148000h to 14BFFFh 14C000h to 14FFFFh 150000h to 153FFFh 154000h to 157FFFh 158000h to 15BFFFh 15C000h to 15FFFFh 160000h to 163FFFh 164000h to 167FFFh 168000h to 16BFFFh 16C000h to 16FFFFh 170000h to 173FFFh 174000h to 177FFFh 178000h to 17BFFFh 17C000h to 17FFFFh 180000h to 183FFFh 184000h to 187FFFh 188000h to 18BFFFh 18C000h to 18FFFFh 190000h to 193FFFh 194000h to 197FFFh 198000h to 19BFFFh 19C000h to 19FFFFh 1A0000h to 1A3FFFh 1A4000h to 1A7FFFh 1A8000h to 1ABFFFh 1AC000h to 1AFFFFh 1B0000h to 1B3FFFh 1B4000h to 1B7FFFh (Continued) 18 MBM29XL12DF-70/80 (Continued) Sector Size Bank Sector (KW / A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) Bank Address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 Bank B SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Sector Address (x 16) Address Range 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3FFFFFh (x 32) Address Range 1B8000h to 1BBFFFh 1BC000h to 1BFFFFh 1C0000h to 1C3FFFh 1C4000h to 1C7FFFh 1C8000h to 1CBFFFh 1CC000h to 1CFFFFh 1D0000h to 1D3FFFh 1D4000h to 1D7FFFh 1D8000h to 1DBFFFh 1DC000h to 1DFFFFh 1E0000h to 1E3FFFh 1E4000h to 1E7FFFh 1E8000h to 1EBFFFh 1EC000h to 1EFFFFh 1F0000h to 1F3FFFh 1F4000h to 1F7FFFh 1F8000h to 1FBFFFh 1FC000h to 1FFFFFh 19 MBM29XL12DF-70/80 Sector Address Tables (Bank C) Sector Size Bank Sector (KW / A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) Bank Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 Bank C SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Sector Address (x 16) Address Range 400000h to 407FFFh 408000h to 40FFFFh 410000h to 417FFFh 418000h to 41FFFFh 420000h to 427FFFh 428000h to 42FFFFh 430000h to 437FFFh 438000h to 43FFFFh 440000h to 447FFFh 448000h to 44FFFFh 450000h to 457FFFh 458000h to 45FFFFh 460000h to 467FFFh 468000h to 46FFFFh 470000h to 477FFFh 478000h to 47FFFFh 480000h to 487FFFh 488000h to 48FFFFh 490000h to 497FFFh 498000h to 49FFFFh 4A0000h to 4A7FFFh 4A8000h to 4AFFFFh 4B0000h to 4B7FFFh 4B8000h to 4BFFFFh 4C0000h to 4C7FFFh 4C8000h to 4CFFFFh 4D0000h to 4D7FFFh 4D8000h to 4DFFFFh 4E0000h to 4E7FFFh 4E8000h to 4EFFFFh 4F0000h to 4F7FFFh 4F8000h to 4FFFFFh 500000h to 507FFFh 508000h to 50FFFFh 510000h to 517FFFh 518000h to 51FFFFh 520000h to 527FFFh 528000h to 52FFFFh 530000h to 537FFFh (x 32) Address Range 200000h to 203FFFh 204000h to 207FFFh 208000h to 20BFFFh 20C000h to 20FFFFh 210000h to 213FFFh 214000h to 217FFFh 218000h to 21BFFFh 21C000h to 21FFFFh 220000h to 223FFFh 224000h to 227FFFh 228000h to 22BFFFh 22C000h to 22FFFFh 230000h to 233FFFh 234000h to 237FFFh 238000h to 23BFFFh 23C000h to 23FFFFh 240000h to 243FFFh 244000h to 247FFFh 248000h to 24BFFFh 24C000h to 24FFFFh 250000h to 253FFFh 254000h to 257FFFh 258000h to 25BFFFh 25C000h to 25FFFFh 260000h to 263FFFh 264000h to 267FFFh 268000h to 26BFFFh 26C000h to 26FFFFh 270000h to 273FFFh 274000h to 277FFFh 278000h to 27BFFFh 27C000h to 27FFFFh 280000h to 283FFFh 284000h to 287FFFh 288000h to 28BFFFh 28C000h to 28FFFFh 290000h to 293FFFh 294000h to 297FFFh 298000h to 29BFFFh (Continued) 20 MBM29XL12DF-70/80 Sector Size Bank Sector (KW / A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) Bank Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 Bank C SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Sector Address (x 16) Address Range 538000h to 53FFFFh 540000h to 547FFFh 548000h to 54FFFFh 550000h to 557FFFh 558000h to 55FFFFh 560000h to 567FFFh 568000h to 56FFFFh 570000h to 577FFFh 578000h to 57FFFFh 580000h to 587FFFh 588000h to 58FFFFh 590000h to 597FFFh 598000h to 59FFFFh 5A0000h to 5A7FFFh 5A8000h to 5AFFFFh 5B0000h to 5B7FFFh 5B8000h to 5BFFFFh 5C0000h to 5C7FFFh 5C8000h to 5CFFFFh 6D0000h to 5D7FFFh 6D8000h to 5DFFFFh 5E0000h to 5E7FFFh 5E8000h to 5EFFFFh 5F0000h to 5F7FFFh 5F8000h to 5FFFFFh 600000h to 607FFFh 608000h to 60FFFFh 610000h to 617FFFh 618000h to 61FFFFh 620000h to 627FFFh 628000h to 62FFFFh 630000h to 637FFFh 638000h to 63FFFFh 640000h to 647FFFh 648000h to 64FFFFh 650000h to 657FFFh 658000h to 65FFFFh 660000h to 667FFFh 668000h to 66FFFFh (x 32) Address Range 29C000h to 29FFFFh 2A0000h to 2A3FFFh 2A4000h to 2A7FFFh 2A8000h to 2ABFFFh 2AC000h to 2AFFFFh 2B0000h to 2B3FFFh 2B4000h to 2B7FFFh 2B8000h to 2BBFFFh 2BC000h to 2BFFFFh 2C0000h to 2C3FFFh 2C4000h to 2C7FFFh 2C8000h to 2CBFFFh 2CC000h to 2CFFFFh 2D0000h to 2D3FFFh 2D4000h to 2D7FFFh 2D8000h to 2DBFFFh 2DC000h to 2DFFFFh 2E0000h to 2E3FFFh 2E4000h to 2E7FFFh 2E8000h to 2EBFFFh 2EC000h to 2EFFFFh 2F0000h to 2F3FFFh 2F4000h to 2F7FFFh 2F8000h to 2FBFFFh 2FC000h to 2FFFFFh 300000h to 303FFFh 304000h to 307FFFh 308000h to 30BFFFh 30C000h to 30FFFFh 310000h to 313FFFh 314000h to 317FFFh 318000h to 31BFFFh 31C000h to 31FFFFh 320000h to 323FFFh 324000h to 327FFFh 328000h to 32BFFFh 32C000h to 32FFFFh 330000h to 333FFFh 334000h to 337FFFh (Continued) 21 MBM29XL12DF-70/80 (Continued) Sector Size Bank Sector (KW / A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) Bank Address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 Bank C SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Sector Address (x 16) Address Range 670000h to 677FFFh 678000h to 67FFFFh 680000h to 687FFFh 688000h to 68FFFFh 690000h to 697FFFh 698000h to 69FFFFh 6A0000h to 6A7FFFh 6A8000h to 6AFFFFh 6B0000h to 6B7FFFh 8B8000h to 6BFFFFh 6C0000h to 6C7FFFh 6C8000h to 6CFFFFh 6D0000h to 6D7FFFh 6D8000h to 6DFFFFh 6E0000h to 6E7FFFh 6E8000h to 6EFFFFh 6F0000h to 6F7FFFh 6F8000h to 6FFFFFh (x 32) Address Range 338000h to 33BFFFh 33C000h to 33FFFFh 340000h to 343FFFh 344000h to 347FFFh 348000h to 34BFFFh 34C000h to 34FFFFh 350000h to 353FFFh 354000h to 357FFFh 358000h to 35BFFFh 35C000h to 35FFFFh 360000h to 363FFFh 364000h to 367FFFh 368000h to 36BFFFh 36C000h to 36FFFFh 370000h to 373FFFh 374000h to 377FFFh 378000h to 37BFFFh 37C000h to 37FFFFh 22 MBM29XL12DF-70/80 Sector Address Tables (Bank D) Sector Size Bank Sector (KW / A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 KDW) Bank Address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 Bank D SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 Sector Address (x 16) Address Range 700000h to 707FFFh 708000h to 70FFFFh 710000h to 717FFFh 718000h to 71FFFFh 720000h to 727FFFh 728000h to 72FFFFh 730000h to 737FFFh 738000h to 73FFFFh 740000h to 747FFFh 748000h to 74FFFFh 750000h to 757FFFh 758000h to 75FFFFh 760000h to 767FFFh 768000h to 76FFFFh 770000h to 777FFFh 778000h to 77FFFFh 780000h to 787FFFh 788000h to 78FFFFh 790000h to 797FFFh 798000h to 79FFFFh 7A0000h to 7A7FFFh 7A8000h to 7AFFFFh 7B0000h to 7B7FFFh 7B8000h to 7BFFFFh 7C0000h to 7C7FFFh 7C8000h to 7CFFFFh 7D0000h to 7D7FFFh 7D8000h to 7DFFFFh 7E0000h to 7E7FFFh 7E8000h to 7EFFFFh 7F0000h to 7F7FFFh 7F8000h to 7F8FFFh 7F9000h to 7F9FFFh 7FA000h to 7FAFFFh 7FB000h to 7FBFFFh 7FC000h to 7FCFFFh 7FD000h to 7FDFFFh 7FE000h to 7FEFFFh 7FF000h to 7FFFFFh (x 32) Address Range 380000h to 383FFFh 384000h to 387FFFh 388000h to 38BFFFh 38C000h to 38FFFFh 390000h to 393FFFh 394000h to 397FFFh 398000h to 39BFFFh 39C000h to 39FFFFh 3A0000h to 3A3FFFh 3A4000h to 3A7FFFh 3A8000h to 3ABFFFh 3AC000h to 3AFFFFh 3B0000h to 3B3FFFh 3B4000h to 3B7FFFh 3B8000h to 3BBFFFh 3BC000h to 3BFFFFh 3C0000h to 3C3FFFh 3C4000h to 3C7FFFh 3C8000h to 3CBFFFh 3CC000h to 3CFFFFh 3D0000h to 3D3FFFh 3D4000h to 3D7FFFh 3D8000h to 3DBFFFh 3DC000h to 3DFFFFh 3E0000h to 3E3FFFh 3E4000h to 3E7FFFh 3E8000h to 3EBFFFh 3EC000h to 3EFFFFh 3F0000h to 3F3FFFh 3F4000h to 3F7FFFh 3F8000h to 3FBFFFh 3FC000h to 3FC7FFh 3FC800h to 3FCFFFh 3FD000h to 3FD7FFh 3FD800h to 3FDFFFh 3FE000h to 3FE7FFh 3FE800h to 3FEFFFh 3FF000h to 3FF7FFh 3FF800h to 3FFFFFh 23 MBM29XL12DF-70/80 Sector Group Address Table Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 A17 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 A16 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A15 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X A14 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 X X X SA8 to SA10 A13 0 0 0 0 1 1 1 1 A12 0 0 1 1 0 0 1 1 A11 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 (Continued) 24 MBM29XL12DF-70/80 Sector Group SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51 SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65 SGA66 SGA67 A21 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A19 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 A18 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A17 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A15 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sectors SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA134 SA135 to SA138 SA139 to SA142 SA143 to SA146 SA147 to SA150 SA151 to SA154 SA155 to SA158 SA159 to SA162 SA163 to SA166 SA167 to SA170 SA171 to SA174 SA175 to SA178 SA179 to SA182 SA183 to SA186 SA187 to SA190 SA191 to SA194 SA195 to SA198 SA199 to SA202 SA203 to SA206 SA207 to SA210 SA211 to SA214 SA215 to SA218 SA219 to SA222 SA223 to SA226 SA227 to SA230 SA231 to SA234 SA235 to SA238 SA239 to SA242 SA243 to SA246 (Continued) 25 MBM29XL12DF-70/80 (Continued) Sector Group SGA68 SGA69 SGA70 SGA71 SGA72 SGA73 SGA74 SGA75 SGA76 SGA77 SGA78 SGA79 A21 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 1 1 1 1 1 1 A19 1 1 1 1 1 1 1 1 1 1 1 1 A18 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 1 1 1 1 1 1 1 1 1 1 A16 0 1 0 1 1 1 1 1 1 1 1 1 A15 X X X 0 0 1 1 1 1 1 1 1 1 1 A14 X X X 0 1 0 1 1 1 1 1 1 1 1 A13 X X X X 0 0 0 0 1 1 1 1 A12 X X X X 0 0 1 1 0 0 1 1 A11 X X X X 0 1 0 1 0 1 0 1 Sectors SA247 to SA250 SA251 to SA254 SA255 to SA258 SA259 to SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 26 MBM29XL12DF-70/80 Common Flash Memory Interface Code Description Query-unique ASCII string "QRY" Primary OEM Command Set 02h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min (write/erase)DQ7 to DQ4=1V, DQ3 to DQ0=100 mV VCC Max (write/erase)DQ7 to DQ4=1V, DQ3 to DQ0=100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/word write 2 s N A6 to A0 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h N DQ15 to DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0018h 0005h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h Typical timeout for Min size buffer write 2 s Typical timeout per individual sector erase 2 ms Typical timeout for full chip erase 2 ms Max timeout for byte/word write 2 times typical s N N N Max timeout for buffer write 2 times typical s N Max timeout per individual sector erase 2 times typical ms Max timeout for full chip erase 2 times typical ms Device Size = 2 byte Flash Device Interface description 05h: x16 / x32 Max number of byte in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z x 256 bytes) Erase Block Region 2 Information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z x 256 bytes) Erase Block Region 3 Information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z x 256 bytes) N N N (Continued) 27 MBM29XL12DF-70/80 (Continued) Description Erase Block Region 4 Information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z x 256 bytes) Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 04h = Required and 0.17m technology Erase Suspend 02h = To Read & Write Sector Protection 00h = Not Supported X = Number of sectors in per group Sector Temporary Unprotection 01h = Supported Sector Protection Algorithm Dual Operation 00h = Not Supported, X = Total number of sectors in all Banks except Bank A Burst Mode Type 00h = Not Supported Page Mode Type 02h = 8 Word Page VACC (Acceleration) Supply Minimum DQ7 to DQ4=1V, DQ3 to DQ0=100 mV VACC (Acceleration) Supply Maximum DQ7 to DQ4=1V, DQ3 to DQ0=100 mV Boot Type Program Suspend, 01h = Supported Bank Organization X = Number of Banks Bank A Region Information X = Number of sectors in Bank A Bank B Region Information X = Number of sectors in Bank B Bank C Region Information X = Number of sectors in Bank C Bank D Region Information X = Number of sectors in Bank D A6 to A0 39h 3Ah 3Bh 3Ch 40h 41h 42h 43h 44h 45h 46h DQ15 to DQ0 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0033h 0004h 0002h 47h 0001h 48h 49h 4Ah 0001h 0007h 00E7h 4Bh 4Ch 4Dh 4Eh 4Fh 50h 57h 58h 59h 5Ah 5Bh 0000h 0002h 00B5h 00C5h 0001h 0001h 0004h 0027h 0060h 0060h 0027h 28 MBM29XL12DF-70/80 s FUNCTIONAL DESCRIPTION Simultaneous Operation The device features functions that enable data reading from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank is selected by bank address ( A21, A20, A19 ) with zero latency. The device consists of the following four banks : Bank A : 8 x 4KW and 31x 32KW; Bank B : 96 x 32 KW; Bank C : 96 x32KW; Bank D : 8 x 4KW and 31 x 32KW. The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks, and Bank 2, a bank consisting of the three remaining banks. See "FlexBankTM Architecture" below. This is what we call "FlexBank", for example the rest of banks B, C and D to let the system read while Bank A is in the process of program (or erase) operation. However the different types of operations for the three banks are not allowed, e.g. Bank A programming, Bank B erasing, and Bank C reading out. With this "FlexBank", as described in "Example of Virtual Banks Combination", the system gets to select from four combinations of data volume for Bank 1 and Bank 2, which works well to meet the system requirement. The simultaneous operation cannot execute multi-function mode in the same bank. Refer to "Bank-to-Bank Read/Write(Program and Erase) Timing Diagram". FlexBankTM Architecture Bank Splits 1 2 3 4 Bank 1 Bank Size 16 Mbit 48 Mbit 48 Mbit 16 Mbit Combination Bank A Bank B Bank C Bank D Bank Size 112 Mbit 80 Mbit 80 Mbit 112 Mbit Bank 2 Combination Bank B, C, D Bank A, C, D Bank A, B, D Bank A, B, C Example of Virtual Banks Combination Bank Splits Bank 1 Bank Size Combination of Memory Bank Sector Sizes Bank Size Bank 2 Combination of Memory Bank Bank B + Bank C + Bank D Bank B + Bank C Bank A + Bank C + Bank D Bank C + Bank D Sector Sizes 1 16 Mbit Bank A 8 x 4K words, 31 x 32K words 112 Mbit 8 x 4K words, 223 x 32K words 2 32 Mbit Bank A + Bank D 16 x 4K words, 62 x 32K words 96 Mbit 192 x 32K words 3 48 Mbit Bank B 96 x 32K words 80 Mbit 16 x 4K words, 158 x 32K words 4 64 Mbit Bank A + Bank B 8 x 4K words, 127 x 32Kwords 64 Mbit 8 x 4K words, 127 x 32Kwords Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out they output the sequence flag once they are selected. Meanwhile the system would get to read from either Bank C or Bank D. 29 MBM29XL12DF-70/80 Simultaneous Operation Case 1 2 3 4 5 6 7 Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode Bank 2 Status Read mode Autoselect mode Program mode Erase mode Read mode Read mode Read mode Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the Banks. Read Mode The device has two control functions required to obtain data at the outputs. CE is the power control and used for a device selection. OE is the output control and used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. Assuming the addresses have been stable for at least tACC - tOE time. When reading out a data without changing addresses after power-up, input hardware reset or to change CE pin from "H" or "L". Page Mode Read The device is capable of fast Page mode read and are compatible with the Page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 8 words or 4 double words, within the appropriate Page being selected by the higher address bits A21 to A2 and the LSB bits A1 to A0 (in the double word mode) and A1 to A-1(in the word mode) determining the specific double word or word within that page. This is an asynchronous operation with the microprocessor supplying the specific double word or word location. The random or initial page access is equal to tACC and subsequent Page read access (as long as the locations specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device and OE is the output control and used to gate data to the output pins if the device is selected. Fast Page mode accesses are obtained by keeping A21 to A2 constant and changing A1 to A0 to select the specific double word or changing A1 to A-1 to select the specific word, within that page. Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC0.3 V. Under this condition the current consumed is less than 5 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even when CE="H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS0.3 V (CE="H" or "L") . Under this condition the current consumed is less than 5 A Max. Once the RESET pin is set high, the device requires tRH as a wake-up time for output to be valid for read access. During standby mode, the output is in the high impedance state regardless of OE input. 30 MBM29XL12DF-70/80 Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of the device data. This is useful in the application such as a handy terminal which requires low power consumption. To activate this mode, the device automatically switches itself to low power mode when addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on this mode. The current consumed is typically 1 A (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are continuously read out. When the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. Output Disable With the OE input is at logic high level (VIH), output from the device is disabled. This causes the output pins to be in a high impedance state. Autoselect Autoselect mode allows reading out of a binary code and identifies its manufacturer and type.It is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes may then be sequenced from the device outputs by toggling addresses. All addresses are DON'T CARES except A6 to A0. The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "Command Definitions Table" of sDEVICE BUS OPERATIONS. In the command Autoselect mode, the bank addresses BA (A21, A20, A19) must point to a specific bank during the third write bus cycle of the Autoselect command. Then the Autoselect data are read from that bank while array data can be read from the other bank. A read cycle from address 00h returns the manufacturer's code (Fujitsu=04h) . A read cycle from address 01h (at word mode, 02h) outputs device code. When 2222227Eh (at word mode, 227Eh) is output, it indicates that two additional codes, called Extended Device Codes is required. Therefore the system may continue reading out these Extended Device Codes at addresses of 0Eh (at word mode, 1Ch) and 0Fh (at word mode, 1Eh). Refer to "Autoselect Codes Table" and "Extended Autoselect Code Table" in sDEVICE BUS OPERATION. In the case of applying VID on A9, because both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation cannot be executed. Write Device erase and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine output dictates the device function. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever starts later, while data is latched on the rising edge of WE or CE, whichever starts first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. 31 MBM29XL12DF-70/80 Double Word/Word Configuration DW/W pin selects double word (32-bit) mode or word (16-bit) mode for the device. When this pin is driven high, device operates in the double word (32-bit) mode. Data is read and programmed at DQ31 to DQ0. When this pin is driven low, device operates in word (16-bit) mode. Under this mode, DQ31/A-1 pin becomes the lowest address bit, and DQ30 to DQ16 bits are tri-stated. However, the command bus cycle is always an 16-bit operation and hence commands are written at DQ15 to DQ0 and DQ31 to DQ16 bits are ignored. Refer to "Double Word Mode Configuration Timing Diagram","Word Mode Configuration Timing Diagram" and "DW/W Diagram for Write Operations" in "sTIMING DIAGRAM". Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group becomes temporarily unprotected. The system uses fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore the present sequence is used for programming and detection of completion during acceleration mode. Removing VACC from the ACC pin and applying VIL or VIH returns the device to normal operation. Do not remove VACC from ACC pin while programming. See "Accelerated Program Timing Diagram". RESET Hardware Reset The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed is terminated and the internal state machine is reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore once the RESET pin goes high the device requires an additional "tRH" before it allows read access. When the RESET pin is low, the device is in the standby mode for the duration of the pulse and all the data output pins are tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location are corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See "RESET, RY/BY Timing Diagram". HiddenROM Region Unlike previous flash memory devices, the MBM29XL12DF allows simultaneous operation while the HiddenROM is enabled. However, there are a number of restrictions associated with simultaneous operation and device operation when the HiddenROM is enabled: (1) The HiddenROM is not available for reading while the Password Unlock, any PPB program/erase operation, or Password programming are in progress. Reading to any location in the Bank A will return the status of these operations until these operations have completed execution. (2) Writing the corresponding Sector Protect latch associated with the overlaid bootblock sector results in the Sector Protect latch NOT being updated. This is only accomplished when the HiddenROM is not enabled. (3) Reading the corresponding DPB associated with the overlaid bootblock sector results in reading invalid data when the PPB Lock/DPB Verify command is issued. This function is only accomplished when the HiddenROM is not enabled. (4) All commands are available for execution when the HiddenROM is enabled except the following list. Issuing the following commands while the HiddenROM is enabled results in the command being ignored. -- CFI -- Set to Fast Mode -- Fast Program -- Reset from Fast Mode -- Program and Sector Erase Suspend -- Program and Sector Erase Resume 32 MBM29XL12DF-70/80 (5) Executing the Sector Erase command is permitted when the HiddenROM is enabled, however, there is no provision for erasing the HiddenROM with the Sector Erase command, regardless of the protection status. The Sector Erase command will erase all other sectors when the HiddenROM is enabled. Erasing the HiddenROM with the Embedded Algorithm is accomplished by issuing the Chip Erase command. If the HiddenROM is the only sector requiring erasure, set the Sector Protect latches for the remaining sectors prior to issuing the Chip Erase command. (6) Executing the HiddenROM Entry command during program or erase suspend mode is allowed. Since the Sector Erase/Program Resume command is disabled while the HiddenROM is enabled, the user cannot resume programming or erase of the HiddenROM in place of the overlaid boot block sector. HiddenROM Protection Bit The HiddenROM Protection Bit prevents programming of the HiddenROM memory area. Once set, the HiddenROM memory area contents are non-modifiable. 33 MBM29XL12DF-70/80 34 MBM29XL12DF-70/80 (4) New Sector Protection [Software Protection] A command sector protection method that replaces the old VID controlled protection method in future. However MBM29XL12DF supports both VID protection and Persistent Sector Protection. Both Protect supported as a shift period. The Persistent Sector Protection and the old VID controlled protection can go back each other until Persistent Protection Lock Bit is settled. a) Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 K words boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure. b) Dynamic Protection Bit (DPB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DPBs is "0". Each DPB is individually modifiable through the DPB Write Command. When the parts are first shipped, the PPBs are cleared, the DPBs are cleared, and PPB Lock is defaulted to power up in the cleared state - meaning the PPBs are changeable. When the device is first powered on the DPBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DPB related to that sector. For the sectors that have the PPBs cleared, the DPBs control whether or not the sector is protected or unprotected. By issuing the DPB Write/Erase command sequences, the DPBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DPBs maybe set or cleared as often as needed. PPB vs DPB The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the NonVolatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PBB Lock to disable any further changes to the PBBs during system operation. The WP write protect pin adds a final level of hardware protection to the two outermost 4K words on both ends of boot sectors. When this pin is low it is not possible to change the contents of these two sectors. These sectors generally hold system boot code. So, the WP pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DPB Write command sequence is all that is necessary. The DPB write/erase command for the dynamic sectors switch the DPBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either 35 MBM29XL12DF-70/80 putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. Note: to achieve the best protection, it's recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP = VIL. DPB 0 1 0 1 0 1 0 1 PPB 0 0 1 1 0 0 1 1 PPB Lock 0 0 0 0 1 1 1 1 Sector State Unprotected--PPB and DPB are changeable Protected--PPB and DPB and DPB are changeable Protected--PPB and DPB and DPB are changeable Protected--PPB and DPB and DPB are changeable Unprotected--PPB not changeable, DPB is changeable Protected--PPB not changeable, DPB is changeable Protected--PPB not changeable, DPB is changeable Protected--PPB not changeable, DPB is changeable The above table contains all possible combinations of the DPB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PBB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DPB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DPB, PPB, and PPB lock for a given sector can be verified by writing a DPB/PPB/PPB lock verify command to the device. -DPB/PPB Status The programming of the DPB/PPB for a given sector can be verified by writing a DPB/PPB status verify command to the device. -PPB Lock Bit Status The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. c) Persistent Protection Bit Lock (PPB Lock) * PPB Locked * PPB Locked with Password A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password protection method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. 36 MBM29XL12DF-70/80 It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The WP Hardware Protection feature is always available, independent of the software managed protection method chosen. A global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates the device is in Password Protection Mode, the PPB Lock Bit is also set after a hardware reset (RESET asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit back to a "1". If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Sector Protection Mode. -Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. Fujitsu recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: (1) It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. (2) It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. 37 MBM29XL12DF-70/80 -Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. (5) Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. While PPB Lock is set, this device cannot enter the Temporary Sector Group Unprotection mode. 38 MBM29XL12DF-70/80 s COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are input into bank reading, the commands have priority over the reading. "MBM29XL12DF Command Definitions Table" in sDEVICE BUS OPERATION shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover, Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ15 to DQ0 and DQ31 to DQ16 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, verify mode of secter protect commands, the Read/Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device automatically powers-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a higher voltage. However multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. The higher order address (A21, A20, A19) required for reading out the manufacture and device codes demands the bank address (BA) set at the third write cycle. Following the command write, a read cycle from address (BA) 00h returns the manufacturer's code (Fujitsu=04h). And, at double word mode, a read cycle at address (BA) 01h (at word mode, 02h) outputs device code. When 2222227Eh (at word mode, 227Eh) is output, this indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh (at word mode, 1Ch), as well as at (BA) 0Fh (at word mode, 1Eh). Refer to "MBM29XL12DF Autoselect Codes Table" and "Exteneded Auteselect Code Table" in sDEVICE BUS OPERATION. The sector state (PPB protection or PPB unprotection) is informed by address (SA) XX02h . Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12 and A11) while(A6, A5, A4, A3, A2, A1,A0) = (0, 1, 1, 1, 0, 1, 0) produces logic "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verifying sector group protection on the protected sector. See "MBM29XL12DF User Bus Operations Table (DW/W = VIL)" and "MBM29XL12DF User Bus Operations Table (DW/W = VIH)" in sDEVICE BUS OPERATION. The manufacture and device codes can be read from the selected bank. To read the manufacture and device codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command sequence into the register. Autoselect command should then be written into the bank to be read. If the software (program code) for Autoselect command is stored in the Flash memory, the device and manufacture codes should be read from the other bank, which does not contain the software. 39 MBM29XL12DF-70/80 To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, Read/Reset command sequence must be written before the Autoselect command. Word/Double Word Programming Command The device is programmed on word-by-word basis (or double word-by-double word). Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device automatically provides adequate internally generated program pulses and verify programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which device returns to the read mode and addresses are no longer latched. See "Hardware Sequence Flags". Therefore the device requires that a valid address to the device be supplied by the system in this particular instance. Hence Data Polling must be performed at the memory location being programmed. Any commands written to the chip during this period are ignored. If hardware reset occurs during the programming operation, the data being written is not guaranteed. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only erase operations can convert from "0"s to "1"s. Refer to "Embedded ProgramTM Algorithm" using typical command strings and bus operations. Program Suspend/Resume Command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation immediately suspends the programming. The Program Suspend command may also be issued during a programming operation while an erase is suspended. The bank addresses of sector being programmed should be set when writing the Program Suspend command. When the Program Suspend command is written during a programming process, the device halts the program operation within 1 s and updates the status bits. After the program operation has been suspended, the system can read data from any address. The data at program-suspended address is not valid. Normal read timing and command definitions apply. After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses of sectors being suspended should be set when writing the Program Resume command. The system can determine the program operation status using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the Autoselect command sequence in the Program Suspend mode. The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits from the Autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Program Resume command (address bits are "Bank Address") to exit from the Program Suspend mode and continue programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming. 40 MBM29XL12DF-70/80 Chip Erase Command Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. (Preprogram Function) The system is not required to provide any controls or timings during these operations. The system can determine the erase operation status by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is "1" (See "Write Operation Status" section.) at which the device returns to read the mode. Chip Erase Time: Sector Erase Time x All sectors + Chip Program Time (Preprogramming) Refer to "Embedded EraseTM Algorithm" for typical command strings and bus operations. Sector Erase Command Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever starts later, while the command (Data = 30h) is latched on the rising edge of CE or WE whichever states first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors are erased concurrently by writing the six bus cycle operations on "MBM29XL12DF Command Definitions Table" in sDEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command is not accepted and erasure does not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE whichever starts first initiates the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever starts first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, "Sector Erase Timer".) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun may corrupt the data in the sector. In that case restart the erase on those sectors and allow them to complete. Refer to "Write Operation Status" section for Sector Erase Timer operation. Loading the sector erase buffer may be done in any sequence and with any number of sectors. Sector erase does not require the user to program prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The sector erase begins after the "tTOW" time out from the rising edge of CE or WE whichever starts first for the last sector erase command pulse and terminates when the data on DQ7 is "1" at which time the device returns to the read mode. See "Write Operation Status" section. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase. In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed. Refer to "Embedded EraseTM Algorithm" for typical command strings and bus operations. 41 MBM29XL12DF-70/80 Erase Suspend/Resume Command The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command is ignored during the Chip Erase operation. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are "DON'T CARES" when writting the Erase Suspend or Erase Resume command.When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum of "tSPD" to suspend the erase operation. When the device has entered the erase-suspended mode, the DQ7 bit is at logic "1", and DQ6 stops toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation is suspended. Further writes of the Erase Suspend command are ignored. When the erase operation is suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode causes DQ2 to toggle. See the section on DQ2. After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode causes DQ2 to toggle. The end of the erase-suspended program operation is detected by the Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular program operation. Note that DQ7 must be read from the program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point is ignored. Another Erase Suspend command is written after the chip resumes erasing. Fast Mode Fast Mode function dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register. In this mode the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. The read operation is also executed after exiting this mode. During the Fast mode, do not write any commands other than the Fast program/ Fast mode reset command. To exit this mode, write Fast Mode Reset command into the command register. Refer to "Embedded Program Algorithm for Fast Mode". The VCC active current is required even CE = VIH during Fast Mode. Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). Refer to "Embedded Program Algorithm for Fast Mode". Query (CFI:Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Refer to "Common Flash Memory Interface Code" in sFLEXIBLE SECTOR-ERASE ARCHITECTURE in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ31 to DQ16) is "0" in word mode (16 bit) read. To terminate operation, write the Read/Reset command sequence into the register. 42 MBM29XL12DF-70/80 HiddenROM Entry Command The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However once it is protected, it is impossible to unprotect. Therefore extreme caution is required. HiddenROM area is 128 words in Bank A. This area is normally the "outermost" 8K words boot block area. Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears. The following commands are permitted after issuing the HiddenROM Entry command: 1. Autoselect 2. Password Program 3. Password Verify 4. Password Unlock 5. Read/Reset 6. Program 7. Chip and Sector Erase 8. HiddenROM Protection Bit Program 9. PPB Program 10. All PPB Erase 11. PPB Lock Bit Set 12. DPB Write 13. DPB/PPB/PPB Lock Bit Verify 14. HiddenROM Exit The following commands are unavailable when the HiddenROM is enabled. Issuing the following commands while the HiddenROM is enabled results in the command being ignored. 1. CFI 2. Set to Fast Mode 3. Fast Program 4. Reset from Fast Mode 5. Program and Sector Erase Suspend 6. Program and Sector Erase Resume The HiddenROM Entry command is allowed when the device is in either program or erase suspend modes. If the HiddenROM is enabled, the program or erase suspend command is ignored. This prevents resuming either programming or erase on the HiddenROM if the overlayed sector is undergoing programming or erase. It is the responsibility of the software to resume the program or erase of a suspended program or erase after exiting the HiddenROM. Executing any of the PPB program/erase commands, or Password Unlock command results in the Bank A returning the status of these operations while they are in progress, thus making the HiddenROM unavailable for reading. If the HiddenROM is enabled while the DPB command is issued, the DPB for the overlayed sector is not updated. Reading the DPB status using the PPB Lock Bit/DPB verify command when the HiddenROM is enabled returns invalid data. 43 MBM29XL12DF-70/80 HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as using the DQ7 data polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other than the HiddenROM area is selected to program, data of the address are changed. HiddenROM Protect Command The method to protect the HiddenROM is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A5, A4, A3, A2, A1, A0) = (0, 1, 1, 1, 0, 1, 0), and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A5, A4, A3, A2, A1, A0) = (0, 0, 1, 1, 0, 1, 0) and the sector address in the HiddenROM area, and read. When "1" appears on DQ0, the protect setting is completed. "0" appears on DQ0 if it is not protected. Please apply write pulse agian. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector protect in the past. And the device has also HiddenROM protect command without VID. See "MBM29XL12DF Command Definitions Table" in sDEVICE BUS OPERATION. Other sector will be effected if the address other than those for HiddenROM area is selected for the sector address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest attention. Another method to protect is to issue HiddenROM Protection Bit Program Command. This is able to protect HiddenROM area by command only. Password Program Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. In word mode, 4 Password Program commands (In double word mode. 2 Password Program commands)are required to program the password. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program Algorithm with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64-bit password combinations are valid as a password. Password Programming is permitted if the HiddenROM is enabled. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. The Password Verify command is permitted if the HiddenROM is enabled. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1:A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. 44 MBM29XL12DF-70/80 Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erase. If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Password Protection Mode Locking Bit Program command is permitted if the HiddenROM is enabled. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Persistent Sector Protection Mode Locking Bit Program command is permitted if the HiddenROM is enabled. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DPBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command. The PPB Lock Bit Set command is permitted if the HiddenROM is enabled. DPB Write(Erase) Command The DPB Write command is used to set or clear a DPB for a given sector. The high order address bits (A21 to A11) are issued at the same time as the code 01h or 00h on DQ7 to DQ0. All other DQ data bus pins are ignored during the data write cycle. The DPBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DPBs are cleared at power-up or hardware reset.Exiting the DPB Write command is accomplished by writing the Read/Reset command. The DPB Write command is permitted if the HiddenROM is enabled. DPB /PPB Verify command DPB/PPB verify command is uesed to verify the status of several sectors. Scanning the sector addresses (SA) will produce a logical "1" at the device output DQ0 for a protected sector. Otherwise the device will produce "0" at DQ0 for the sector which is not protected. The DPB/PPB verify erify command is permitted if the HiddenROM is enabled. PPB Lock Bit Verify command PPB Lock Bit verify command is used to verify the status of a PPB Lock Bit. A logical "1" at the device output DQ1 indicates that the PPB Lock Bit is set. If PPB Lock Bit is not set, DQ1 will output"0".The PPB Lock Bit verify command is permitted if the HiddenROM is enabled. 45 MBM29XL12DF-70/80 Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. A0 and A1 are used to determine the 16 bit data quantity is used to match separated 16 bits. Writing the Password Unlock command is address order specific. In other words, the lowers address A1:A0 = 00, the next cycle command is to A1:A0 = 01, then to A1:A0 = 10, and finally to A1:A0 = 11. Writing out of sequence results in the Password Unlock not returning a match with the password and the PPB Lock Bit remains set. Once the Password Unlock command is entered, the RY/BY pin goes LOW indicating that the device is busy. Also, reading the Bank A results in the DQ6 pin toggling, indicating that the Password Unlock function is in progress. Reading the other bank returns actual array data. Approximately 1s is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY is not driven and DQ6 does not toggle when read), the next cycle is issued, only this time with the next part of the password. Seven cycles Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RY/BY signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock cycles, the order, and when to read the PPB Lock bit to confirm successful password unlock. The Password Unlock command is permitted if the HiddenROM is enabled. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A21 to A11) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. The PPB Program command is permitted if the HiddenROM is enabled. The PPB Program command does not follow the Embedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased with-out margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. The All PPB Erase command is permitted if the HiddenROM is enabled. 46 MBM29XL12DF-70/80 Write Operation Status Detailed in "Hardware Sequence Flags" are all the status flags which can determine the status of the bank for the current mode operation. The read operation from the bank which doesn't operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is properly completed. The information on DQ2 is address-sensitive. This means that if an address from an erasing sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase and which are not. The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank >, [2] < non-busy bank >, [3] < busy bank >, the DQ6 toggles in the case of [1] and [3]. In case of [2], the data of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in [1] and [3]. Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Suspended In Progress Mode Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Program Suspended Mode Program Suspend Read (Program Suspended Sector) Program Suspend Read (Non-Program Suspended Sector) DQ7 DQ7 0 1 Data DQ7 Data Data DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle Data Data Toggle Toggle Toggle DQ5 0 0 0 Data 0 Data Data 1 1 1 DQ3 0 1 0 Data 0 Data Data 0 1 0 DQ2 1 Toggle*1 Toggle Data 1*2 Data Data 1 N/A N/A Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode *1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2: Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. Notes: * DQ0 and DQ1 are reserve pins for future use. * DQ4 is limited to Fujitsu internal use. DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device will produce a "1" on DQ7. The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm". 47 MBM29XL12DF-70/80 For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that device is driving status information on DQ7 at one instant, and then that byte's valid data at the next instant. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to DQ7 will be read on successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See "Toggle Bit Status" and "Data Polling during Embedded Algorithm Operation Timing Diagram". DQ6 Toggle Bit I The device also features the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequences. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 1 s and then stop toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data kept remained. Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle. To operate toggle bit function properly, CE or OE must be high when bank address is changed. See "AC Wavefrom for Toggle Bit I during Embedded Algorithm Operations". DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce "1". This is a failure condition indicating that the program or erase cycle was not successfully completed. Data Polling is only operating function of the device under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in "MBM29XL12DF User Bus Operations Table (DW/W = VIL)" and "MBM29XL12DF User Bus Operations Table (DW/W = VIH)" in sDEVICE BUS OPERATION. 48 MBM29XL12DF-70/80 The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset device with the command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun. If DQ3 is low ("0") , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags". DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Toggle Bit Status" and "DQ2 vs DQ6". Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system 49 MBM29XL12DF-70/80 tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to "Toggle Bit Algorithm". Toggle Bit Status Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle * Toggle 1* * : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. RY/BY (Ready/Busy Pin) The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device is placed in an Erase Suspend mode, RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during RESET pulse. Refer to the following detailed timing diagrams. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state machine to Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequence. Device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min). If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) can not be used. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Power-up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. 50 MBM29XL12DF-70/80 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground. All pins except A9, OE, RESET and ACC *1, *2 Power Supply Voltage *1, *2 A9, OE, RESET and ACC *1, *3 *1 : Voltage is defined on the basis of VSS=GND=0V. *2 : Minimum DC voltage on input or l/O pins is -0.5 V. During voltage transitions, inputs or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC +0.5 V. During voltage transitions,inputs may overshoot to VCC +2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE, RESET and ACC pins is -0.5 V. During voltage transitions, A9, OE, RESET and ACC pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE, RESET and ACC pins is +13.0 V which may overshoot to +14.0V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol Tstg TA VIN, VOUT VCC VIN Rating Min -55 -40 -0.5 -0.5 -0.5 Max +125 +85 VCC+0.5 +4.0 +13.0 Unit C C V V V s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature Power Supply Voltage * Symbol TA VCC Part No. MBM29XL12DF-70/80 MBM29XL12DF-70 MBM29XL12DF-80 Value Min -40 +3.0 +2.7 Max +85 +3.6 +3.1 Unit C V V * : Voltage is defined on the basis of VSS=GND=0V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 51 MBM29XL12DF-70/80 s MAXIMUM OVERSHOOT / MAXIMUM UNDERSHOOT +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Maximum Undershoot Waveform 20 ns VCC +2.0 V VCC +0.5 V +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC +0.5 V 20 ns 20 ns Note: This waveform is applied for A9, OE, RESET, and ACC. Maximum Overshoot Waveform 2 52 MBM29XL12DF-70/80 s DC CHARACTERISTICS Value Parameter Input Leakage Current Output Leakage Current A9, OE, RESET, ACC Inputs Leakage Current ACC Accelerated Program Current Symbol ILI ILO ILIT ILIA Conditions Min VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = Vcc Max VCC = VCC Max, A9, OE, RESET, ACC= 12.5V VCC = VCC Max, ACC = VACC Max CE = VIL, OE = VIH f = 10MHz ICC1 CE = VIL, OE = VIH f = 5MHz ICC2 ICC3 CE = VIL, OE = VIH VCC = VCC Max, CE = VCC 0.3 V, RESET =VCC 0.3 V, WP = VCC 0.3 V VCC = VCC Max, RESET =VSSQ 0.3 V CE = VIL, OE = VIH, f = 40MHz VCC = VCC Max, CE = VSS 0.3 V, RESET =VCC 0.3 V VIN = VCC 0.3 V or VSS 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH -- -- -- -- -- 1 35 35 5 mA mA A -1.0 -1.0 -- -- -- Typ -- -- -- -- -- Max +1.0 +1.0 35 20 70 A A A mA mA Unit VCC Active Current * (Initial/Random Read) 1 VCC Active Current *2 VCC Current (Standby) VCC Current (Standby,Reset) VCC Current (Page Mode) *3 VCC Current (Automatic Sleep Mode) *4 VCC Active Current*6 (Read-While-Program) VCC Active Current*6 (Read-While-Erase) VCC Active Current*6 (Erase-Suspend-Program) ICC4 ICC5 -- -- 1 -- 5 15 A mA ICC6 -- 1 5 A ICC7 ICC8 ICC9 -- -- -- -- -- -- 50 50 35 mA mA mA (Continued) 53 MBM29XL12DF-70/80 (Continued) Value Parameter Input Low Voltage Input High Voltage *5 Voltage for Auteselect and Sector Protection(A9, OE, RESET)*7 Voltage for ACC Program Acceleration Output Low Voltage Output High Voltage VOH2 Low VCC Lock-Out Voltage VLKO IOH = -100 A, VCC = VCC Min -- VCC-0.2 2.3 -- 2.4 -- 2.5 V V Symbol VIL VIH VID VACC VOL VOH1 Conditions Min -- -- -- -- IOL = 4.0 mA, VCC = VCC Min IOH = -2.0 mA, VCC = VCC Min -0.5 VCC-0.2 11.5 11.5 -- VCC-0.4 Typ -- -- 12.0 12.0 -- -- Max 0.6 VCC+0.3 12.5 12.5 0.45 -- V V V V V V Unit *1 : lCC current listed includes both the DC operating current and the frequency dependent component. *2 : lCC active while Embedded Algorithm (Program or Erase) is in progress. *3 : Addresses except A1, A0, (A-1) are fixed. *4 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *5 : About VIH Min , it should be applied larger voltage. *6 : Embedded Algorithm (Program or Erase) is in progress.(@5 MHz) *7 : VID is only for Sector Group Protection operation and Autoselect mode. 54 MBM29XL12DF-70/80 s AC CHARACTERISTICS * Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Page Read Cycle Time Page Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Address, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode Symbol JEDEC tAVAV tAVQV -- -- tELQV tGLQV tEHQZ tGHQZ tAXQX -- Standard tRC tACC tPRC tPACC tCE tOE tDF tDF tOH tREADY -- CE = VIL OE = VIL -- CE = VIL OE = VIL OE = VIL -- -- -- -- -- Value * Condition Min 70 -- 25 -- -- -- -- -- 4 -- 70 Max -- 70 -- 25 70 25 25 25 -- 20 Min 80 -- 30 -- -- -- -- -- 5 -- 80 Max -- 80 -- 30 80 30 30 30 -- 20 ns ns ns ns ns ns ns ns ns ns Unit * : Test Conditions : Output Load: VCC = 2.7 V to 3.1 V :1 TTL gate and 30pF (MBM29XL12DF-70/80) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or VCC Timing measurement reference level Input: 0.5 x VCC Output: 0.5 x VCC 55 MBM29XL12DF-70/80 * Write (Erase/Program) Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling -- -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- 2 3 Symbol JEDEC Standard tAVAV tAVWL -- tWLAX -- tDVWH tWHDX tWC tAS tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP tCSP Min 70 0 12 45 0 35 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 -- -- -- 50 500 500 4 100 4 4 Value 70 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 6 0.5 -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MIn 80 0 12 45 0 45 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 -- -- -- 50 500 500 4 100 4 4 80 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 6 0.5 -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s s s ns ns s s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Double Word Word Sector Erase Operation*1 VCC Setup Time Rise Time to VID *2 Rise Time to VACC* Voltage Transition Time * Write Pulse Width*2 OE Setup Time to WE Active*2 CE Setup Time to WE Active* 2 -- -- -- -- (Continued) 56 MBM29XL12DF-70/80 (Continued) Parameter Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time DW/W Switching Low to Output High-Z DW/W Switching High to Output Active -- -- -- -- -- -- -- -- -- Symbol JEDEC Standard tRB tRP tRH tBUSY tEOE tTOW tSPD tFLQZ tFHQV Min 0 500 200 -- -- 50 -- -- 70 Value 70 Typ -- -- -- -- -- -- -- -- -- Max -- -- -- 90 70 -- 20 30 -- Min 0 500 200 -- -- 50 -- -- 80 80 Typ -- -- -- -- -- -- -- -- -- Max -- -- -- 90 80 -- 20 30 -- ns ns ns ns ns s s ns ns Unit *1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is limited for Accelerated Program operation only. 57 MBM29XL12DF-70/80 s ERASE AND PROGRAMMING PERFORMANCE Value Parameter Min Sector Erase Time Double Word Programming Time Word Programming Time Chip Programming Time Erase/Program Cycle -- -- -- -- 100,000 Typ 0.5 12 6 50.3 -- Max 2 150 s 100 200 -- s cycle s Excludes programming time prior to erase Excludes system-level overhead Excludes system-level overhead -- Unit Comments Notes : * Typical Erase Conditions: TA = +25C, VCC = 2.9 V * Typical Program Conditions: TA = +25C, VCC = 2.9 V, Data = Checker s SSOP PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Value Typ 7.0 6.0 7.5 Max 10.0 12.0 11.0 Unit pF pF pF Notes : * Test Conditions: TA = +25C, f = 1.0 MHz * DQ31/A-1 pin capacitance is stipulated by Output Capacitance. s FBGA PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance Note : Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ TBD TBD TBD Max TBD TBD TBD Unit pF pF pF * Test Conditions: TA = +25C, f = 1.0 MHz * DQ31/A-1 pin capacitance is stipulated by Output Capacitance. 58 MBM29XL12DF-70/80 s TIMING DIAGRAM * Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L": Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Change from H to L Will Be Change from L to H Changing, State Unknown Center Line is HighImpedance "Off" State tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tCE tOH Outputs High-Z Output Valid High-Z Read Operation Timing Diagram 59 MBM29XL12DF-70/80 A21 to A2 Same Page Address A1 to A0 (A-1) Aa tRC tACC Ab tPRC Ac tPRC Ad CE tCE OE tOEH tOE tDF WE High-Z tPACC tOH tPACC tOH tPACC tOH tOH Outputs Da Db Dc Dd Page Read Operation Timing Diagram tRC Address tACC Address Stable CE tRH tRP tRH tCE RESET tOH High-Z Outputs Outputs Valid Hardware Reset/Read Operation Timing Diagram 60 MBM29XL12DF-70/80 CE Rising edge of the last WE signal WE Entire program or erase operations RY/BY tBUSY RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET tRP tRB RY/BY tREADY RESET, RY/BY Timing Diagram 61 MBM29XL12DF-70/80 3rd Bus Cycle Address 555h tWC tAS PA tAH Data Polling PA tRC CE tCS tCH tCE OE tGHWL tWP tWPH tWHWH1 tOE WE tDS tDH tDF tOH Data A0h PD DQ7 DOUT DOUT Notes: * PA is address of the memory location to be programmed. * PD is data to be programmed at word address (x16 mode). * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence. * These waveforms are for the x32 mode. (The addresses differ from x16 mode.) Alternate WE Controlled Program Operation Timing Diagram 62 MBM29XL12DF-70/80 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH PD DQ7 DOUT Data A0h Notes: * PA is address of the memory location to be programmed. * PD is data to be programmed at word address (x16 mode). * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence. * These waveforms are for the x32 mode. (The addresses differ from x16 mode.) Alternate CE Controlled Program Operation Timing Diagram 63 MBM29XL12DF-70/80 Address 555h tWC 2AAh tAS tAH 555h 555h 2AAh SA* CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 10h for Chip Erase 10h/ 30h Data tVCS VCC * : SA is the sector address for Sector Erase. Address = 555h (Double Word). AAAh (Word) for Chip Erase. Note : These waveforms are for the x32 mode. (The addresses differ from x16 mode.) Chip/Sector Erase Operation Timing Diagram 64 MBM29XL12DF-70/80 CE t CH t OE t DF OE t OEH WE t CE * DQ7 Data DQ7 DQ7 = Valid Data High-Z t WHWH1 or 2 DQ6 to DQ0 Data DQ6 to DQ0 = Output Flag t EOE DQ6 to DQ0 Valid Data High-Z * : DQ7 = Valid Data (The device has completed the Embedded operation.) Data Polling during Embedded Algorithm Operation Timing Diagram 65 MBM29XL12DF-70/80 Address tAHT tASO tAHT tAS CE tCEPH WE tOEH tOEPH tOEH OE tDH tOE tCE DQ 6/DQ2 Data tBUSY Toggle Data Toggle Data Toggle Data * Stop Toggling Output Valid RY/BY *: DQ6 stops toggling (The device has completed the Embedded operation.) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations 66 MBM29XL12DF-70/80 Read tRC Command tWC Read tRC Command tWC Read tRC Read tRC Address BA1 tAS BA2 (555h) tAH BA1 tACC tCE BA2 (PA) BA1 tAS tAHT BA2 (PA) CE tOE tCEPH OE tGHWL tWP tOEH tDF WE tDS tDH tDF DQ Valid Output Valid Intput (A0h) Valid Output Valid Intput (PD) Valid Output Status Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 Bank-to-Bank Read / Write(Program and Erase) Timing Diagram Enter Embedded Erase Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE Erase Suspend Read DQ6 DQ2 * Toggle DQ2 and DQ6 with OE or CE * : DQ2 is read from the erase-suspended sector. DQ2 vs. DQ6 67 MBM29XL12DF-70/80 CE tCE DW/W DQ30 to DQ0 tELFH Data Output (DQ15 to DQ0) tFHQV A-1 Data Output (DQ30 to DQ0) DQ31/A-1 DQ31 Double Word Mode Configuration Timing Diagram CE DW/W tELFL DQ30 to DQ0 Data Output (DQ30 to DQ0) tACC Data Output (DQ15 to DQ0) DQ31/A-1 DQ31 tFLQZ A-1 Word Mode Configuration Timing Diagram Falling edge of the last write signal CE or WE DW/W tSET (tAS) Input Valid tHOLD (tAH) DW/W Timing Diagram for Write Operations 68 MBM29XL12DF-70/80 Address (A21 to A11) SPAX SPAY A6, A2, A0 A5, A4, A3, A1 VID VIH A9 VID VIH OE tVLHT tVLHT tWPP tVLHT tVLHT WE tOESP CE tCSP Data tVCS tOE 01h VCC SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected Note : A-1 is VIL in word mode. Sector Group Protection Timing Diagram 69 MBM29XL12DF-70/80 VCC tVCS tVIDR tVLHT VID VIH RESET CE WE tVLHT Program Command Sequence tVLHT RY/BY Unprotection period Temporary Sector Group Unprotection Timing Diagram 70 MBM29XL12DF-70/80 VCC VID VIH tVCS RESET Address tVLHT tVIDR tWC tWC SGAX SGAX SGAY A6, A2, A0 A5, A4, A3, A1 CE OE tWP TIME-OUT WE Data 60h 60h 40h tOE 01h 60h SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min) Extended Sector Group Protection Timing Diagram 71 MBM29XL12DF-70/80 VCC tVCS VACC VIH ACC tVACCR tVLHT CE WE tVLHT Program Command Sequence Acceleration period tVLHT Accelerated Program Timing Diagram 72 MBM29XL12DF-70/80 EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling Device Embedded Program Algorithm in progress Verify Data ? Yes No No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes : * The sequence is applied for x32 mode. * The addresses differ from x16 mode. Embedded ProgramTM Algorithm 73 MBM29XL12DF-70/80 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling or Toggle Bit from Device No Data = FFh ? Yes Erasure Completed Embedded Erase Algorithm in progress Chip Erase Command Sequence (Address/Command): 555h/AAh Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address/30h Sector Address/30h Additional sector erase commands are optional. Sector Address/30h Note : The sequence is applied for x32 mode. The addresses differ from x16 mode. Embedded EraseTM Algorithm 74 MBM29XL12DF-70/80 Start Read DQ7 to DQ0 Addr. = VA DQ7 = Data? No No DQ5 = 1? Yes Read DQ7 to DQ0 Addr. = VA Yes VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erase operation. = Any of the sector addresses within the sector not being protected during chip erase operation. DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Data Polling Algorithm 75 MBM29XL12DF-70/80 Start VA = Bank address being excuted Embedded Algorithm *1 Read DQ7 to DQ0 Addr. = VA Read DQ7 to DQ0 Addr. = VA *1 DQ6 = Toggle? Yes No No DQ5 = 1? Yes Read DQ7 to DQ0 Addr. = VA *1, *2 Read DQ7 to DQ0 Addr. = VA *1, *2 DQ6 = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command No Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to "1". Toggle Bit Algorithm 76 MBM29XL12DF-70/80 Start Setup Sector Group Addr. (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT = 1 OE = VID, A9 = VID, CE = VIL, RESET = VIH A6 = A2 = A0 = VIL, A5 = A4 = A3 = A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 s WE = V IH, CE = OE = V IL (A9 should remain VID) Read from Sector Group (Addr. = SPA, A6 = A2 = A0 = VIL, A5 = A4 = A3 = A1 = VIH ) * No No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command Data = 01h? Yes Yes Protect Another Sector Group ? No Remove VID from A9 Write Reset Command Device Failed Sector Group Protection Completed * : A-1 is VIL in word mode. Sector Group Protection Algorithm 77 MBM29XL12DF-70/80 Start RESET = VID *1 Perform Erase or Program Operation RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sector groups are unprotected. *2 : All previously protected sector groups are reprotected once again. Temporary Sector Group Unprotection Algorithm 78 MBM29XL12DF-70/80 Start RESET = VID Wait to 4 s Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Sector Group Write 60h to SGA A6 = A2 = A0 = VIL, A5 = A4 = A3 = A1 =VIH Time out 250 s To Verify Sector Group Protection Write 40h to SGA A6 = A2 = A0 = VIL, A5 = A4 = A3 = A1=VIH ( ) Increment PLSCNT ( ) No Read from Sector Group Address (Addr. = SGA, A6 = A2 = A0 = VIL, A5 = A4 = A3 = A1 = VIH)* Setup Next SGA No Data = 01h? Yes Protect Other Sector Group? No Remove VID from RESET Write Reset Command Yes PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Device Failed Sector Group Protection Completed * : A-1 is VIL in word mode. Extended Sector Group Protection Algorithm 79 MBM29XL12DF-70/80 FAST MODE ALGORITHM Start 555h/AAh 2AAh/55h Set Fast Mode 555h/20h XXXh/A0h Program Address/Program Data Data Polling Device In Fast Program Verify Data? Yes No Increment Address Last Address ? Yes Programming Completed No BA/90h Reset Fast Mode XXXh/F0h Embedded Program Algorithm for Fast Mode 80 MBM29XL12DF-70/80 Start HiddenROM Entry PPB Program Operation DQ 0 = 1? Yes HiddenROM Exit No HiddenROM Exit Yes Protect Another ? No PPB Protection Completed PPB Protection Algorithm 81 MBM29XL12DF-70/80 Start HiddenROM Entry DPB Program Operation Yes Protect Another ? No HiddenROM Exit DPB Protection Algorithm 82 MBM29XL12DF-70/80 Start Start HiddenROM Entry Read Auto-select DPB/PPB & PPB Lock Bit Status Command DPB/PPB PPB lock bit PPB Bit Status DQ0 = 0 (Unprotected) DQ0 = 1 (Protected) PPB Protection Status DQ0 = 0 (Unprotected) DQ0 = 1 (Protected) Note: This output indicates the "OR" between DPB and PPB DQ1 = 0 (Unprotected) DQ1 = 1 (Protected) Note: This output indicates PPB lock bit DPB/PPB & PPB Lock Bit Status Protection Status 83 MBM29XL12DF-70/80 Start Addr. = AAAh Data = AAh HiddenROM Entry Addr. = 555h Data = 55h repeat 4-times Addr. = AAAh Data = 38h Password Program Operation * Password Verify Addr. = XX0h to XX3h Data = PD0 to PD3 HiddenROM Exit * : Password Program (word mode) Password Mode Set 84 MBM29XL12DF-70/80 Password Mode Choice Method Start Password Program Password Verify Password Protection Mode Bit Program No (Time out) DQ0 = 0? Yes Reset Command Reset Command Yes Correct? No Reset Command Program Complete Password Sector Protect Algorithm 85 MBM29XL12DF-70/80 PPB Lock Clear in Password Mode Start Password Unlock Password Unlock No (Time out) RY/BY = H? Yes No DPB/PPB/PPB Lock Bit Status DQ0 = 1? Yes Password/Unlock Complete Reset Command All PPB Erase No (Time out) DQ0 = 0? Yes Program Complete Reset Command PPB Lock Bit Clear in Password Mode 86 MBM29XL12DF-70/80 s ORDERING INFORMATION MBM29XL12D F 70 PFV PACKAGE TYPE PFV = 90-pin Shrink Outline L-leaded Package (SSOP) PBT = 96-ball Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See "Product Selector Guide". DEVICE REVISION DEVICE NUMBER/DESCRIPTION MBM29XL12D 128 Mega-bit (8M x 16-Bit or 4M x 32-Bit) Page Mode Flash Memory 3.0 V-only Read, Program, and Erase Part Number MBM29XL12DF 70PFV MBM29XL12DF 80PFV MBM29XL12DF 70PBT MBM29XL12DF 80PBT Package 90-pin plastic SSOP (FPT-90P-M01) 96-ball plastic FBGA (BGA-96P-M02) Access Time (ns) 70 80 70 80 Remarks 87 MBM29XL12DF-70/80 s PACKAGE DIMENSIONS 90-pin plastic SSOP (FPT-90P-M01) Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. *1 23.700.30(.933.012) 90 46 1.800.10 (Mounting height) (.071.004) 0.550.10 (Stand off) (.022.004) "A" 16.000.30 (.630.012) *213.300.20 (.524.008) INDEX 1 45 Details of "A" part M 0.50(.020) 0.220.05 (.009.002) 0.08(.003) 0.17 .007 +0.05 -0.03 +.002 -.001 0~8 0.88 -0.15 .035 -.006 +0.12 +.005 0.25(.010) 0.08(.003) C 2003 FUJITSU LIMITED F90001S-c-2-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 88 MBM29XL12DF-70/80 (Continued) 96-ball plastic FBGA (BGA-96P-M02) 14.500.10(.571.004) 1.05 -0.10 .041-.004 +0.15 +.006 (Mounting height) 0.380.10 (Stand off) (.015.004) 0.40(.016) REF B 0.40(.016) REF 0.80(.031) REF 11 10 9 8 7 6 5 4 3 2 1 RQPNMLKJHGFEDCBA 0.80(.031) REF 9.500.10 (.374.004) A 0.10(.004) S INDEX AREA S 96-o0.450.05 (96-o.018.002) INDEX SIDE 0.08(.003) M SAB C 2003 FUJITSU LIMITED B96002S-c-1-1 Dimensions in mm (inches) Note : The values in parentheses are reference values. 89 MBM29XL12DF-70/80 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0307 (c) FUJITSU LIMITED Printed in Japan |
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